ARTEMiS-SSN Inlined Time-stamped Bridge in Two-level VSC-based HVDC Applications

Abstract

SSN simulation of VSC-HVDC with Inlined Voltage Inverter Compensation (IVIC)​ The circuit shows the capability of ARTEMiS-SSN to accurately simulate 2-level Voltage Source Converter (VSC)-HVDC circuits ARTEMiS-SSN incorporates a novel interpolation algorithm for 2-level inverters very similar to averaging inverter model with interpolation (also called Time-Stamped Bridge -TSB). The main difference between this model and TSB is that there is NO DECOUPLING DELAY between the inverter and the rest of the circuit. In some circuit like VSC-HVDC, a delay-free solution is mandatory to obtain an accurate simulation at relatively large time step. Also, not only the 'Inlined TSB' compensates for the output voltage, it also does compensate the bridge input current, a critical aspect in this demo. In this demo, the sample is 20us, PWM frequency is 1950 Hz and a dead-time of 2 us is applied to the PWM firing. Simulation shows that current and voltage amplitudes have a negligible jitter. [Inverter DC/AC; Voltage source converter (VSC); High Voltage Direct Current (HVDC); Dead-time; Protection:Delay; Pulse width modulation (PWM) ]